1. Field of the Invention
The present invention relates to a memory management system and an image processing apparatus that enable efficient management of a cache memory in a multiprocessor system having a plurality of processors, a cache memory, and a shared memory.
2. Description of the Related Art
To improve the processing performance of a processor, a cache memory that enables high speed access is provided between a main memory (main storage area) that has a slow working speed and the processor, to thereby reduce the frequency at which the processor accesses the main memory.
The systems for writing data to a cache memory include a write through system and a write back system. The write through system is a system that writes to both the cache memory and the main memory when a write to the main memory occurs.
The write back system is a system in which, when a write to the main memory occurs, writing is first performed to only the cache memory, and then writing is performed to the main memory. Since the write back system can shorten the write time in addition to the readout time, it can make full use of the high speed properties of a cache memory. However, in the write back system it is necessary to execute control to maintain the coherency of data between the cache memory and the main memory. For example, when flushing (releasing) data of the cache memory and the like, it is necessary to write back the data of the cache memory to the main memory after invalidating the cache memory.
As technology that shortens the time required for invalidation when invalidating a cache memory, a cache memory device has been proposed that sequentially reads out the tag addresses of all cache lines using a counter that generates a line index, checks whether the tag addresses correspond to the range of set addresses, and invalidates the corresponding cache lines.
In a multi-core system that includes a plurality of microprocessors, when a cache memory is provided for each of the cores it is necessary to provide a mechanism that maintains the coherency of data between a shared memory and a cache memory and between a cache memory and a cache memory. Cache management technology that is directed at a common multi-core system has been proposed, such as in Japanese Patent Laid-Open No. 2005-148771, that incorporates a mechanism that manages an exclusive access as well as a shared state.
However, with respect to a data access pattern in image processing, since a characteristic that specification is possible based on information such as parameters is not utilized prior to actually accessing the data because of the characteristic that image processing is data flow processing (in particular, with respect to decoding processing of dynamic images), the spatial locality and temporal locality of memory accesses of an image processing program can not be adequately utilized. Therefore, there is a problem that the utilization efficiency of the cache memory is lowered.
As a method to compensate for a lowering in the utilization efficiency of the cache memory, technology for obtaining cache information and finding any duplication of the cache information based on image block information also exists to thereby improve the utilization efficiency. However, when hardware for making a duplication decision is used in a multi-core system with more than four cores it is necessary to provide hardware that detects duplication for combinations of 4×4=16, and thus the technology cannot be utilized because the scale increases.